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A4984 DMOS Microstepping Driver with Translator and Overcurrent Protection
Features and Benefits
Low RDS(ON) outputs Automatic current decay mode detection/selection Mixed and Slow current decay modes Synchronous rectification for low power dissipation Internal UVLO Crossover-current protection 3.3 and 5 V compatible logic supply Thin profile QFN and TSSOP packages Thermal shutdown circuitry Short-to-ground protection Shorted load protection Low current Sleep mode, < 10 A No smoke no fire (NSNF) compliance (ET package)
Approximate size
Description
The A4984 is a complete microstepping motor driver with built-in translator for easy operation. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes. Step modes are selectable by MSx logic inputs. It has an output drive capacity of up to 35 V and 2 A. The A4984 includes a fixed off-time current regulator which has the ability to operate in Slow or Mixed decay modes. The ET package meets customer requirements for no smoke no fire (NSNF) designs by adding no-connect pins between critical output, sense, and supply pins. So, in the case of a pin-to-adjacent-pin short, the device does not cause smoke or fire. Additionally, the device does not cause smoke or fire when any pin is shorted to ground or left open. The translator is the key to the easy implementation of the A4984. Simply inputting one pulse on the STEP input drives the motor one microstep. There are no phase sequence tables, high frequency control lines, or complex interfaces to program. The A4984 interface is an ideal fit for applications where a complex microprocessor is unavailable or is overburdened. During stepping operation, the chopping control in the A4984 automatically selects the current decay mode, Slow or Mixed.
Continued on the next page...
Packages:
24-contact QFN with exposed thermal pad 4 mm x 4 mm x 0.75 mm (ES package)
with exposed thermal pad
5 mm x 5 mm x 0.90 mm (ET package) 24-pin TSSOP with exposed thermal pad (LP Package)
32-contact QFN
Typical Application Diagram
VDD 0.22 F VREG ROSC VDD 5 k Microcontroller or Controller Logic SLEEP STEP MS1 MS2 DIR ENABLE RESET VREF GND
0.1 F
0.1 F
0.22 F
CP1
CP2
VCP
VBB1 VBB2 OUT1A 100 F
A4984
OUT1B SENSE1
OUT2A OUT2B GND SENSE2
4984-DS
A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
Description (continued) In Mixed decay mode, the device is set initially to a fast decay for a proportion of the fixed off-time, then to a slow decay for the remainder of the off-time. Mixed decay current control results in reduced audible motor noise, increased step accuracy, and reduced power dissipation. Internal synchronous rectification control circuitry is provided to improve power dissipation during PWM operation. Internal circuit protection includes: thermal shutdown with hysteresis, undervoltage lockout (UVLO), and crossover-current protection. Special power-on sequencing is not required. The A4984 is supplied in three surface mount packages: two QFN packages, the 4 mm x 4 mm, 0.75 mm nominal overall height ES package, and the 5 mm x 5 mm x 0.90 mm ET package. The LP package is a 24-pin TSSOP. All three packages have exposed pads for enhanced thermal dissipation, and are lead (Pb) free (suffix -T), with 100% matte tin plated leadframes.
Selection Guide
Part Number A4984SESTR-T A4984SETTR-T A4984SLPTR-T Package 24-pin QFN with exposed thermal pad 32-pin QFN with exposed thermal pad 24-pin TSSOP with exposed thermal pad Packing 1500 pieces per 7-in. reel 1500 pieces per 7-in. reel 4000 pieces per 13-in. reel
Absolute Maximum Ratings
Characteristic Load Supply Voltage Output Current Logic Input Voltage Logic Supply Voltage VBBx to OUTx Sense Voltage Reference Voltage Operating Ambient Temperature Maximum Junction Storage Temperature VSENSE VREF TA TJ(max) Tstg Range S Symbol VBB IOUT VIN VDD Notes Rating 35 2 -0.3 to 5.5 -0.3 to 5.5 35 0.5 5.5 -20 to 85 150 -55 to 150 Units V A V V V V V C C C
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
Functional Block Diagram
0.22 F VREG ROSC CP1
0.1 F CP2
VDD
Current Regulator
OSC
Charge Pump VCP 0.1 F DMOS Full Bridge
REF DAC
VBB1
OUT1A OUT1B PWM Latch Blanking Mixed Decay OCP SENSE1 Gate Drive
STEP DIR RESET MS1 MS2 Translator
DMOS Full Bridge
VBB2
RS1
Control Logic OCP
OUT2A OUT2B
ENABLE SLEEP DAC
PWM Latch Blanking Mixed Decay
SENSE2
RS2
VREF
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
Symbol Test Conditions Operating During Sleep Mode Operating Source Driver, IOUT = -1.5 A Sink Driver, IOUT = 1.5 A Source Diode, IF = -1.5 A Sink Diode, IF = 1.5 A fPWM < 50 kHz Operating, outputs disabled Sleep Mode fPWM < 50 kHz Outputs off Sleep Mode Min. 8 0 3.0 - - - - - - - - - - VDD0.7 VIN = VDD0.7 - -20 -20 - - 5 0.7 20 23 0 -3 - - - 100 2.1 - - 2.7 - Typ.2 - - - 320 320 - - - - - - - - - - <1.0 <1.0 100 50 11 1 30 30 - 0 - - - 475 - 165 15 2.8 90 Max. 35 35 5.5 430 430 1.3 1.3 4 2 10 8 5 10 - VDD0.3 20 20 - - 19 1.3 40 37 4 3 15 5 5 800 - - - 2.9 - Units V V V m m V V mA mA A mA mA A V V A A k k % s s s V A % % % ns A C C V mV
ELECTRICAL CHARACTERISTICS1 at TA = 25C, VBB = 35 V (unless otherwise noted)
Characteristics Output Drivers Load Supply Voltage Range Logic Supply Voltage Range Output On Resistance Body Diode Forward Voltage
VBB VDD RDSON VF IBB
Motor Supply Current
Logic Supply Current Control Logic Logic Input Voltage Logic Input Current Microstep Select Logic Input Hysteresis Blank Time Fixed Off-Time Reference Input Voltage Range Reference Input Current Current Trip-Level Error3 Crossover Dead Time Protection Overcurrent Protection Threshold4 Thermal Shutdown Temperature Thermal Shutdown Hysteresis VDD Undervoltage Lockout VDD Undervoltage Hysteresis
1For 2Typical
IDD
VIN(1) VIN(0) IIN(1) IIN(0) RMS1 RMS2 VHYS(IN) tBLANK tOFF VREF IREF
errI
VIN = VDD0.3 MS1 pin MS2 pin As a % of VDD OSC = VDD or GND ROSC = 25 k
VREF = 2 V, %ITripMAX = 38.27% VREF = 2 V, %ITripMAX = 70.71% VREF = 2 V, %ITripMAX = 100.00%
tDT IOCPST TTSD TTSDHYS VDDUVLO VDDUVLOHYS
VDD rising
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the specified maximum and minimum limits. 3V ERR = [(VREF/8) - VSENSE] / (VREF/8).
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic Package Thermal Resistance Symbol RJA Test Conditions* ES package; estimated, on 4-layer PCB, based on JEDEC standard ET package; estimated, on 4-layer PCB, based on JEDEC standard LP package; on 4-layer PCB, based on JEDEC standard *In still air. Additional thermal information available on Allegro Web site. Value Units 37 32 28 C/W C/W C/W
Maximum Power Dissipation, PD(max)
5.5 5.0 4.5 4.0
R
JA
Power Dissipation, PD (W)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
=
32
C
R
/W
JA
=
28
R
JA
C
/W
=3
7
C/
W
20
40
60
80 100 120 Temperature (C)
140
160
180
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
tA
tB
STEP
tC MSx RESET, or DIR tD
Time Duration STEP minimum, HIGH pulse width STEP minimum, LOW pulse width Setup time, input change to STEP Hold time, input change to STEP Figure 1. Logic Interface Timing Diagram
Symbol tA tB tC tD
Typ. 1 1 200 200
Unit s s ns ns
Table 1. Microstep Resolution Truth Table
MS1 L H L H MS2 L L H H Microstep Resolution Full Step Half Step Quarter Step Eighth Step Excitation Mode 2 Phase 1-2 Phase W1-2 Phase 2W1-2 Phase
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
Functional Description
Device Operation. The A4984 is a complete microstepping motor driver with a built-in translator for easy operation with minimal control lines. It is designed to operate bipolar stepper motors in full-, half-, quarter-, and eighth-step modes. The currents in each of the two output full-bridges and all of the N-channel DMOS FETs are regulated with fixed off-time PWM (pulse width modulated) control circuitry. At each step, the current for each full-bridge is set by the value of its external current-sense resistor (RS1 and RS2), a reference voltage (VREF), and the output voltage of its DAC (which in turn is controlled by the output of the translator). At power-on or reset, the translator sets the DACs and the phase current polarity to the initial Home state (shown in figures 8 through 11), and the current regulator to Mixed Decay Mode for both phases. When a step command signal occurs on the STEP input, the translator automatically sequences the DACs to the next level and current polarity. (See table 2 for the current-level sequence.) The microstep resolution is set by the combined effect of the MSx inputs, as shown in table 1. When stepping, if the new output levels of the DACs are lower than their previous output levels, then the decay mode for the active full-bridge is set to Mixed. If the new output levels of the DACs are higher than or equal to their previous levels, then the decay mode for the active full-bridge is set to Slow. This automatic current decay selection improves microstepping performance by reducing the distortion of the current waveform that results from the back EMF of the motor. according to the ROSC configuration and the step sequence, as shown in figures 8 through 11. During Mixed decay, when the trip point is reached, the A4984 initially goes into a fast decay mode for 31.25% of the off-time, tOFF . After that, it switches to Slow decay mode for the remainder of tOFF. A timing diagram for this feature appears on the next page. Typically, mixed decay is only necessary when the current in the winding is going from a higher value to a lower value as determined by the state of the translator. For most loads automatically-selected mixed decay is convenient because it minimizes ripple when the current is rising and prevents missed steps when the current is falling. For some applications where microstepping at very low speeds is necessary, the lack of back EMF in the winding causes the current to increase in the load quickly, resulting in missed steps. This is shown in figure 2. By pulling the ROSC pin to ground, mixed decay is set to be active 100% of the time, for both rising and falling currents, and prevents missed steps as shown in figure 3. If this is not an issue, it is recommended that automatically-selected mixed decay be used, because it will produce reduced ripple currents. Refer to the Fixed Off-Time section for details.
Low Current Microstepping. Intended for applications
where the minimum on-time prevents the output current from regulating to the programmed current level at low current steps. To prevent this, the device can be set to operate in Mixed decay mode on both rising and falling portions of the current waveform. This feature is implemented by shorting the ROSC pin to ground. In this state, the off-time is internally set to 30 s. Reset Input ( ). The input sets the translator RESET RESET to a predefined Home state (shown in figures 8 through 11), and turns off all of the FET outputs. All STEP inputs are ignored until the input is set to high. RESET
Microstep Select (MSx). The microstep resolution is set by
the voltage on logic inputs MSx, as shown in table 1. The MS1 pin has a 100 k pull-down resistance, and the MS2 pin has a 50 k pull-down resistance. When changing the step mode the change does not take effect until the next STEP rising edge. If the step mode is changed without a translator reset, and absolute position must be maintained, it is important to change the step mode at a step position that is common to both step modes in order to avoid missing steps. When the device is powered down, or reset due to TSD or an over current event the translator is set to the home position which is by default common to all step modes.
Step Input (STEP). A low-to-high transition on the STEP
input sequences the translator and advances the motor one increment. The translator controls the input to the DACs and the direction of current flow in each winding. The size of the increment is determined by the combined state of the MSx inputs.
Mixed Decay Operation. The bridge operates in Mixed decay mode, at power-on and reset, and during normal running
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
Slow Decay Mixed Decay Slow Decay Mixed Decay Slow Decay Mixed Decay Slow Decay Mixed Decay
Missed Step
Voltage on ROSC terminal 2 V/div.
Step input 10 V/div.
t , 1 s/div.
Figure 2. Missed steps in low-speed microstepping
Mixed Decay No Missed Steps
ILOAD 500 mA/div.
Step input 10 V/div.
t , 1 s/div.
Figure 3. Continuous stepping using automatically-selected mixed stepping (ROSC pin grounded)
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
Blanking. This function blanks the output of the current sense
comparators when the outputs are switched by the internal current control circuitry. The comparator outputs are blanked to prevent false overcurrent detection due to reverse recovery currents of the clamp diodes, and switching transients related to the capacitance of the load. The blank time, tBLANK (s), is approximately tBLANK 1 s
Direction Input (DIR). This determines the direction of rotation of the motor. Changes to this input do not take effect until the next STEP rising edge.
Internal PWM Current Control. Each full-bridge is controlled by a fixed off-time PWM current control circuit that limits the load current to a desired value, ITRIP . Initially, a diagonal pair of source and sink FET outputs are enabled and current flows through the motor winding and the current sense resistor, RSx. When the voltage across RSx equals the DAC output voltage, the current sense comparator resets the PWM latch. The latch then turns off either the source FET (when in Slow decay mode) or the sink and source FETs (when in Mixed decay mode).
The maximum value of current limiting is set by the selection of RSx and the voltage at the VREF pin. The transconductance function is approximated by the maximum value of current limiting, ITripMAX (A), which is set by ITripMAX = VREF / ( 8
Shorted-Load and Short-to-Ground Protection.
If the motor leads are shorted together, or if one of the leads is shorted to ground, the driver will protect itself by sensing the overcurrent event and disabling the driver that is shorted, protecting the device from damage. In the case of a short-to-ground, the LEEP device will remain disabled (latched) until the S input goes high or VDD power is removed. A short-to-ground overcurrent event is shown in figure 4. When the two outputs are shorted together, the current path is through the sense resistor. After the blanking time (1 s) expires, the sense resistor voltage is exceeding its trip value, due to the overcurrent condition that exists. This causes the driver to go into a fixed off-time cycle. After the fixed off-time expires the driver turns on again and the process repeats. In this condition the driver is completely protected against overcurrent events, but the short is repetitive with a period equal to the fixed off-time of the driver. This condition is shown in figure 5. If the driver is operating in Mixed decay mode, it is normal for the positive current to spike, due to the bridge going in the forward direction and then in the negative direction, as a result of the direction change implemented by the Mixed decay feature. This is shown in figure 6. In both instances the overcurrent circuitry is protecting the driver and prevents damage to the device.
RS )
where RS is the resistance of the sense resistor () and VREF is the input voltage on the REF pin (V). The DAC output reduces the VREF output to the current sense comparator in precise steps, such that Itrip = (%ITripMAX / 100)
x ITripMAX
(See table 2 for %ITripMAX at each step.) It is critical that the maximum rating (0.5 V) on the SENSE1 and SENSE2 pins is not exceeded.
Fixed Off-Time. The internal PWM current control circuitry uses a one-shot circuit to control the duration of time that the DMOS FETs remain off. The off-time, tOFF, is determined by the ROSC terminal. The ROSC terminal has three settings:
Charge Pump (CP1 and CP2). The charge pump is used to generate a gate supply greater than that of VBB for driving the source-side FET gates. A 0.1 F ceramic capacitor, should be ROSC tied to VDD -- off-time internally set to 30 s, decay connected between CP1 and CP2. In addition, a 0.1 F ceramic mode is automatic Mixed decay except when in full step where capacitor is required between VCP and VBB, to act as a reservoir decay mode is set to Slow decay for operating the high-side FET gates. ROSC tied directly to ground -- off-time internally set to Capacitor values should be Class 2 dielectric 15% maximum, 30 s, current decay is set to Mixed decay for both increasing and decreasing currents, except in full step where decay mode or tolerance R, according to EIA (Electronic Industries Alliance) is set to Slow decay. (See Low Current Microstepping section.) specifications. ROSC through a resistor to ground -- off-time is determined VREG (VREG). This internally-generated voltage is used to operby the following formula, the decay mode is automatic Mixed ate the sink-side FET outputs. The VREG pin must be decoupled decay for all step modes. with a 0.22 F ceramic capacitor to ground. VREG is internally tOFF ROSC 825 monitored. In the case of a fault condition, the FET outputs of the
Where tOFF is in s. A4984 are disabled.
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
5 A / div.
Capacitor values should be Class 2 dielectric 15% maximum, or tolerance R, according to EIA (Electronic Industries Alliance) specifications. Enable Input ( ). This input turns on or off all of the ENABLE FET outputs. When set to a logic high, the outputs are disabled. When set to a logic low, the internal control enables the outputs as required. The translator inputs STEP, DIR, and MSx, as well as the internal sequencing logic, all remain active, independent of the input state. ENABLE
Fault latched
Shutdown. In the event of a fault, overtemperature (excess TJ)
or an undervoltage (on VCP), the FET outputs of the A4984 are disabled until the fault condition is removed. At power-on, the UVLO (undervoltage lockout) circuit disables the FET outputs and resets the translator to the Home state. Sleep Mode ( ). To minimize power consumption SLEEP when the motor is not in use, this input disables much of the internal circuitry including the output FETs, current regulator, LEEP and charge pump. A logic low on the S pin puts the A4984 into Sleep mode. A logic high allows normal operation, as well as start-up (at which time the A4984 drives the motor to the Home microstep position). When emerging from Sleep mode, in order to allow the charge pump to stabilize, provide a delay of 1 ms before issuing a Step command.
t
Figure 4. Short-to-ground event
5 A / div. Fixed off-time
t
Figure 5. Shorted load (OUTxA OUTxB) in Slow decay mode
Mixed Decay Operation. The bridge can operate in Mixed Decay mode, depending on the step sequence, as shown in figures 8 through 11. As the trip point is reached, the A4984 initially goes into a fast decay mode for 31.25% of the off-time, tOFF. After that, it switches to Slow Decay mode for the remainder of tOFF. A timing diagram for this feature appears in figure 7. Synchronous Rectification. When a PWM-off cycle is
triggered by an internal fixed-off time cycle, load current recirculates according to the decay mode selected by the control logic. This synchronous rectification feature turns on the appropriate FETs during current decay, and effectively shorts out the body diodes with the low FET RDS(ON). This reduces power dissipation significantly, and can eliminate the need for external Schottky diodes in many applications. Synchronous rectification turns off when the load current approaches zero (0 A), preventing reversal of the load current.
5 A / div. Fixed off-time
Fast decay portion (direction change) t
Figure 6. Shorted load (OUTxA OUTxB) in Mixed decay mode
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A4984
VSTEP
100.00 70.71
DMOS Microstepping Driver with Translator and Overcurrent Protection
See Enlargement A
IOUT
0
-70.71 -100.00
Enlargement A
toff IPEAK tFD tSD
Slow Decay
IOUT
Mixed Decay
Fa
st
De
ca
y
t
Symbol toff IPEAK tSD tFD IOUT Device fixed off-time Maximum output current Slow decay interval Fast decay interval Device output current Characteristic
Figure 7. Current Decay Modes Timing Chart
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
Application Layout
Layout. The printed circuit board should use a heavy groundplane. For optimum electrical and thermal performance, the A4984 must be soldered directly onto the board. On the underside of the A4984 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB. In order to minimize the effects of ground bounce and offset issues, it is important to have a low impedance single-point ground, known as a star ground, located very close to the device. By making the connection between the pad and the ground plane directly under the A4984, that area becomes an ideal location for a star ground point. A low impedance ground will prevent ground bounce during high current operation and ensure that the supply voltage remains stable at the input terminal.
The two input capacitors should be placed in parallel, and as close to the device supply pins as possible. The ceramic capacitor (C7) should be closer to the pins than the bulk capacitor (C2). This is necessary because the ceramic capacitor will be responsible for delivering the high frequency current components.The sense resistors, RSx , should have a very low impedance path to ground, because they must carry a large current while supporting very accurate voltage measurements by the current sense comparators. Long ground traces will cause additional voltage drops, adversely affecting the ability of the comparators to accurately measure the current in the windings. The SENSEx pins have very short traces to the RSx resistors and very thick, low impedance traces directly to the star ground underneath the device. If possible, there should be no other components on the sense circuits.
A4984
Solder Trace (2 oz.) Signal (1 oz.) Ground (1 oz.) Thermal (2 oz.)
PCB
OUT2B OUT2A OUT1A OUT1B
Thermal Vias
GND
OUT2B
R4 R5 GND
OUT2A
OUT1A
OUT1B
R4 C7
OUT2A SENSE2 OUT1A VBB2 SENSE1
R5
C7
U1
OUT2B ENABLE GND
VBB1 OUT1B DIR GND REF STEP SLEEP VDD
PAD
C3
C1 C6 C3 C4 GND ROSC BULK C2 CAPACITANCE VDD VBB GND
CP1 CP2 VREG
A4984
RESET ROSC MS1 MS2
C4
VCP
C1
C6
ROSC VDD VBB
C2
ES package configuration shown
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
OUT2B C3 U1 GND C5 ROSC C1 C4 C6 GND OUT2A R4 R5 OUT1A GND
GND
C3 C4 C5
CP1 CP2 VCP VREG MS1 MS2 RESET ROSC SLEEP VDD STEP REF
A4984
GND ENABLE OUT2B VBB2
PAD
SENSE2 OUT2A OUT1A SENSE1 VBB1 OUT1B DIR GND
C6 R4
ROSC
BULK GND GND GND CAPACITANCE C2 VDD VBB GND OUT1B
R5
C1
C2 VBB
VDD
LP package typical application and circuit layout
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13
A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
Pin Circuit Diagrams
VDD
VBB
VBB 40 V
VCP
CP1
CP2
8V GND GND
GND PGND GND 8V GND GND GND
VBB VREG SENSE DMOS Parasitic GND VREG
10 V GND
MSx DIR VREF ROSC SLEEP
VBB OUT DMOS Parasitic DMOS Parasitic GND GND
8V GND
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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A4984
STEP
100.00 70.71
DMOS Microstepping Driver with Translator and Overcurrent Protection
STEP
100.00 70.71
Mixed* Slow Slow Mixed Slow Mixed
Home Microstep Position
Home Microstep Position
-70.71 -100.00 100.00 70.71
Home Microstep Position
-70.71 -100.00 100.00 70.71
Mixed* Slow Mixed
Slow Slow Mixed Mixed
Slow
Phase 2 IOUT2A Direction = H (%)
0.00
Slow
-70.71
Phase 2 IOUT2B Direction = H (%)
0.00
-70.71 -100.00
-100.00
*With ROSC pin tied to GND
DIR= H
Figure 8. Decay Mode for Full-Step Increments
STEP
100.00 92.39 70.71 38.27
DIR= H
Figure 9. Decay Modes for Half-Step Increments
Mixed* Slow Mixed
Home Microstep Position
Phase 1 IOUT1A Direction = H (%)
Slow
Mixed
Slow
0.00
-38.27 -70.71 -92.39 -100.00 100.00 92.39 70.71 38.27
Mixed* Slow Mixed Slow Mixed Slow Mixed
Phase 2 IOUT2B Direction = H (%)
0.00
-38.27 -70.71 -92.39 -100.00
*With ROSC pin tied to GND
DIR= H
Figure 10. Decay Modes for Quarter-Step Increments
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
Home Microstep Position
Phase 1 IOUT1A Direction = H (%)
Slow
0.00
Phase 1 IOUT1A Direction = H (%)
Mixed
0.00
15
A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
STEP
100.00 92.39 83.15 70.71 55.56
-38.27 -55.56 -70.71 -83.15 -92.39 -100.00 100.00 92.39 83.15 70.71 55.56
Home Microstep Position
Phase 1 IOUT1A Direction = H (%)
38.27 19.51 0.00 -19.51
Mixed* Slow Mixed Slow Mixed
Phase 2 IOUT2B Direction = H (%)
38.27 19.51 0.00 -19.51 -38.27 -55.56 -70.71 -83.15 -92.39 -100.00
Mixed* Mixed Slow Mixed Slow
*With ROSC pin tied to GND
DIR= H
Figure 11. Decay Modes for Eighth-Step Increments
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A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
Table 2. Step Sequencing Settings
Home microstep position at Step Angle 45; DIR = H
Phase 1 Current
[% ItripMax]
Full Step #
Half Step # 1
1/4 Step # 1
1/8 Step # 2 2
Phase 2 Current
[% ItripMax]
(%) 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80 0.00 -9.80 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -92.39 -95.69 -98.08 -99.52
(%) 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52 100.00 99.52 98.08 95.69 92.39 88.19 83.15 77.30 70.71 63.44 55.56 47.14 38.27 29.03 19.51 9.80
Step Angle () 0.0 5.6 11.3 16.9 22.5 28.1 33.8 39.4 45.0 50.6 56.3 61.9 67.5 73.1 78.8 84.4 90.0 95.6 101.3 106.9 112.5 118.1 123.8 129.4 135.0 140.6 146.3 151.9 157.5 163.1 168.8 174.4
Full Step #
Half Step # 5
1/4 Step # 9
1/8 Step # 17 18
Phase 1 Current
[% ItripMax]
Phase 2 Current
[% ItripMax]
Step Angle
()
(%)
-100.00 -99.52 -98.08 -95.69 -92.39 -88.19 -83.15 -77.30 -70.71 -63.44 -55.56 -47.14 -38.27 -29.03 -19.51 -9.80 0.00 9.80 19.51 29.03 38.27 47.14 55.56 63.44 70.71 77.30 83.15 88.19 92.39 95.69 98.08 99.52
(%) 0.00 -9.80 -19.51 -29.03 -38.27 -47.14 -55.56 -63.44 -70.71 -77.30 -83.15 -88.19 -92.39 -95.69 -98.08 -99.52 -100.00 -99.52 -98.08 -95.69 -92.39 -88.19 -83.15 -77.30 -70.71 -63.44 -55.56 -47.14 -38.27 -29.03 -19.51 -9.80
180.0 185.6 191.3 196.9 202.5 208.1 213.8 219.4 225.0 230.6 236.3 241.9 247.5 253.1 258.8 264.4 270.0 275.6 281.3 286.9 292.5 298.1 303.8 309.4 315.0 320.6 326.3 331.9 337.5 343.1 348.8 354.4
2
3 4
10
19 20
1
2
3
5 6
3
6
11
21 22
4
7 8
12
23 24
3
5
9 10
7
13
25 26
6
11 12
14
27 28
2
4
7
13 14
4
8
15
29 30
8
15 16
16
31 32
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
17
A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
Pin-out Diagrams
ES Package
23 SENSE2 20 SENSE1 22 OUT2A 21 OUT1A 24 VBB2 19 VBB1
ET Package
32 SENSE2 31 NC 30 OUT2A 29 NC 28 NC 27 OUT1A 26 NC 25 SENSE1
LP Package
CP1 1 CP2 2 24 23 22 21 20 19 18 OUT1B NC VBB1 NC VCP 3 VREG 4 MS1 5 MS2 6 RESET 7 ROSC 8 SLEEP 9 VDD 10 STEP 11 REF 12 PAD
24 GND 23 ENABLE 22 OUT2B 21 VBB2 20 SENSE2 19 OUT2A 18 OUT1A 17 SENSE1 16 VBB1 15 OUT1B 14 DIR 13 GND
OUT2B ENABLE GND CP1 CP2 VCP
1 2 3 4 5 6 RESET 10 SLEEP 12 ROSC 11 PAD
18 OUT1B 17 DIR 16 GND 15 REF 14 STEP 13 VDD
OUT2B NC VBB2 NC ENABLE GND CP1 CP2
1 2 3 4 5 6 7 8
PAD
DIR GND REF 17 STEP VDD 16
7
8
9
Terminal List Table
Number Name ES CP1 CP2 DIR ENABLE GND MS1 MS2 NC OUT1A OUT1B OUT2A OUT2B REF RESET ROSC SENSE1 SENSE2 SLEEP STEP VBB1 VBB2 VCP VDD VREG PAD 4 5 17 2 3, 16 8 9 - 21 18 22 1 15 10 11 20 23 12 14 19 24 6 13 7 - ET* 7 8 20 5 6, 19 11 12 2, 4, 21, 23, 26, 28, 29, 31 27 24 30 1 18 13 14 25 32 15 17 22 3 9 16 10 - LP 1 2 14 23 13, 24 5 6 - 18 15 19 22 12 7 8 17 20 9 11 16 21 3 10 4 - Charge pump capacitor terminal Charge pump capacitor terminal Logic input Logic input Ground Logic input Logic input No connection DMOS Full Bridge 1 Output A DMOS Full Bridge 1 Output B DMOS Full Bridge 2 Output A DMOS Full Bridge 2 Output B Gm reference voltage input Logic input Timing set Sense resistor terminal for Bridge 1 Sense resistor terminal for Bridge 2 Logic input Logic input Load supply Load supply Reservoir capacitor terminal Logic supply Regulator decoupling terminal Exposed pad for enhanced thermal dissipation* Description
*The GND pins must be tied together externally by connecting to the PAD ground plane under the device.
VCP 9 VREG 10 MS1 11 MS2 12 RESET 13 ROSC 14 SLEEP 15
MS1
VREG
MS2
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
18
A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
ES Package, 24-Pin QFN with Exposed Thermal Pad
0.30 4.00 0.15 24 1 2 A 4.00 0.15 0.95 1 2 2.70 4.10 24 0.50
2.70 4.10 25X D 0.08 C +0.05 0.25 -0.07 0.50 BSC SEATING PLANE 0.75 0.05 C C PCB Layout Reference View
For Reference Only; not for tooling use (reference JEDEC MO-220WGGD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P400X400X80-25W6M) All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals
0.45 MAX
B 2.70 2 1 24 2.70
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
19
A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
ET Package, 32-Contact QFN with Exposed Thermal Pad
5.00 0.15 32 1 2 A 5.00 0.15 1.00 1 2
0.30 32
0.50
3.40
5.00
1 33X D 0.08 C 0.250.10 0.50 BSC SEATING PLANE 0.90 0.10 C 3.40 5.00
C
PCB Layout Reference View
0.500.10 3.40 2 1 32 3.40 B
For Reference Only; not for tooling use (reference JEDEC MO-220VHHD-6) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 QFN50P500X500X100-33V6M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
20
A4984
DMOS Microstepping Driver with Translator and Overcurrent Protection
LP Package, 24-Pin TSSOP with Exposed Thermal Pad
7.80 0.10 24 4 4 +0.05 0.15 -0.06
0.45
0.65
B 3.00 A 4.40 0.10 6.40 0.20 0.60 0.15 (1.00) 3.00 6.10
1
2 4.32 0.25 SEATING PLANE 0.65 1.20 MAX 0.15 MAX C SEATING PLANE GAUGE PLANE 1.65 C
4.32 PCB Layout Reference View
24X 0.10 C +0.05 0.25 -0.06
For Reference Only; not for tooling use (reference JEDEC MO-153 ADT) Dimensions in millimeters Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown A Terminal #1 mark area B Exposed thermal pad (bottom surface) C Reference land pattern layout (reference IPC7351 TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Copyright (c)2008-2010, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
21

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